Package org.vishia.fpga

Interface Summary

Interface	Description
FpgaModule_ifc

Class Summary

Class	Description
Fpga	This class contains hardware related opeations for FPGA simulation which are also accepted by the Java2Vhdl translator.

Annotation Types Summary

Annotation Type	Description
Fpga.BITVECTOR	Defines an numeric variable in VHDL as BIT_VECTOR( DOWNTO 0) This allows only specific routines in this class or assignments.
Fpga.ClockedInput	Defines that an input pin of the Fpga or of an module should be clocked immediately.
Fpga.GetterVhdl	Defines that an Operation is existing in the module class to access data from RECORD instance (associated to a PROCESS).
Fpga.IfcAccess	Defines a sub module in another module which is only responsible to implement an interface as access point to the containing module.
Fpga.STDVECTOR	Defines an numeric variable in VHDL as STD_LOGIC_VECTOR( DOWNTO 0) This is necessary if numeric operations are done.
Fpga.VHDL_PROCESS	Defines an numeric variable in VHDL as STD_LOGIC_VECTOR( DOWNTO 0) This is necessary if numeric operations are done.