Spe Adapter 10 Mbit/s Physical standard / fast communication cycle (downto 50 µs) / SPI interface

The SpeA card is firstly recommended to use in a Ring topology for specific stations without using a switch for fast data transfer with the data on the fly principle. It gets its data immediately before transmission on SPE from the RAM of the controller via SPI access (Serial Peripheral Interface) and it writes received data immediately after receiving via SPI to the RAM of the controller. The controller can prepare the data just in time before transmission and immediately after receive to get a small as possible delay of the whole signal processing (less dead time in a controlling loop). That is the main approach of usage. For that the SpeA-card and the controller should be prepared by programming of course.

If the SpeA-card is Master in a Ring, it expected the echo of the telegram in the ring in a deterministic time. But the delay depends on the number of stations in the ring and the delays in the cable. The receiving data are synchronized with the transmission data to read and write one word via SPI simultaneously. The correspond received word is at least one 16 bit delayed, of course, maybe more as 16 bit steps on longer delays.

This mode is intended for a controller as station in the ring which is not enough powerful for fast SPI access with DMA. It means the data cannot be fast transferred from and to the RAM via SPI. The station should be a slave in the SPE-Ring. It means it forwards received data to the transmitter without the controller. Only a few data words are stored in the FPGA from the received telegram and read from a FPGA-register to replace few data words in the forward transmitted telegram. The controller can access this registers via SPI in a slow way.

This mode allows the immediately connection to a PC net in context of data exchange between controller with a high time accuracy. The cycle time for the data exchange can be 1..2 ms due to the transfer rate of 10 Mbit/s and a telegram length of 800..1500 Byte. 1 till 2 milliseconds is a proper value for synchronized mechanical movements, but also for fast second level electrical control.

It is necessary to use an extra Ethernet card on the PC for this approach, because this Slot should transfer with 10 Mbit/s full duplex. The integration in a local PC net is possible, if the router transfer the data after the immediately 10 Mbit/s plug with an higher speed, it means a special router should realize the 10 Mbit/s baud rate.

See SPE ring topology with PC connection

For this operation mode only one connection is intended to use. The SpeA card and the controller should be programmed normally as SPE-slave, the SPI should be prepared. The received data from a telegram are written in the RAM of the controller via fast SPI access. After the telegram an interrupt should be triggered which tests the data. If the data are proper for an answer, the SpeA-card and the controller should be programmed one time as SPE-master, transmit the answer (the line should be in gap state before), and after transmission immediately the card should be programmed again as SPE-slave for receiving. For this operation mode the controller should be fast act for this network data transfer. It is not the best divide solution for evaluation the data on PHY chip level.

If the SpeA-card with the FPGA works in Star or Bus Topology or as Master in Ring topology, then it is always Master. The time of the telegram is determined by the controller, which initializes the SPI for the data transfer and outputs the frame_in signal to start the telegram.

This is similar as the mode before. The difference is, the data are stored in the FPGA. Maybe also answer data can be stored and automatically answered (depending on the content of the FPGA). The received data and answer data can be read and written in a slow cycle via SPI access from the controller as master. This mode is intended to use for a less powerful controller as station.

Another possibility of usage is: The SpeA-card is a participant on a multi drop line or it is connected to a switch. It is prepared to receive data. The data will be written immediately to the RAM of the controller.

A SpeA-card which is not connected to the controller, or the controller is in reset or crashed after reset, the SpeA-card should act as SPE-Ring Slave. This is important because the communication in the Ring should not depend on the proper work of any station in the ring. On faulty the ring should primary work.

Only the dedicated master in the ring can be determined by hardware to prevent this SPE-Ring Slave forward transmission. This is necessary because otherwise a life of its own can occur: A telegram can be generated and circle continuously in the ring. The master functionality breaks this forward transportation, and the ring is silent if the master is silent.

The hardware determination for master is a jumper (connection) between J3.9 (FPGA pin A16) and J3.10 (GND).

Without using the frame_in signal, held it inactive low, the SPEa-card can be accessed for all configuration and data register via SPI, whereby the controller is master of SPI, the SpeA-card is slave.

You see here soldering points which can be also a pin-header for Power supply, SPI, and the Frame signals.

Right side you have a VCC (3.3 V) plug, and above the adequate 5P plug for 5 V. Left of that there are two ground plugs. Then to the left, the lower raw contains the 3.3 V pins, which are immediately connected to the FPGA pins. The pins exactly above are the correspond pins for 5 V level. There is one pin outside. This is a second input for SPI if the SPE-Adapter card is SPI-Slave as MOSI with 5 V level.

Some controller have a logic level of 5 V due to the older definitions of TTL interface or also CMOS. This Pins, usually immediate the controller pins, must not connect to the 3.3 V-level pins of the SPE-Adapter card. For this approach a potential adaption is existing. Hence, only the upper row should be used, or the bottom (lower) row, depending on the kind of the processor pin level.

The image above shows a part of the FPGA wiring, especially 5 V inputs.

The 5 V outputs are driven with open drain and pullup:

The "cheap" solution with simple voltage divider and open-drain driver is used, because it is though sufficient and the application for 5 V is not the important one. The open drain outputs are available without additinal effort because some gather for the current source switching are otherwise unused. The effort for an otherwise necessary extra driver circuit is saved.

The 470 Ohm pullup causes a rising edge time of ~ 25 ns on 50 pF parasitic capacity load. This capacity can be occur on longer connection lines to your hardware. But usual it should be lesser, so that 20 ns are not reached. The signals has pulse widths of 50 ns for the SPI clock. So the rising time for the 5 V signals is near the limit but admissible.

The 470 Ohm pullup forces a 10 mA current from the power supply for low level. Hence it is more sufficient to have a inactive high level (as it is usual for the classic TTL signal approaches, "low active". If the 5 V outputs are not used as in many applications, this current can be prevented by two mechanism:

If the outputs are used also as inputs and hence as outputs for the controller, especially for SC5 and SI5S connected to SO5, then the output of the controller may need drive 10 mA to low. But the resistor of 470 Ohm is possible to switch off for this mode. The pin S5P on FPGA (B3) should be set to low for this mode.

The following 5-V signals are driven with this logic:

For combination of this signal see also chapter SPE card in passive and active mode, with same MOSI and MISO

If the SPE card is in active mode and Frame_in ⇒ 1 then the SPE cards starts immediately a SPI data transfer with the SPE card as master. Hence the controller should be programmed as SPI slave with a data rate of 10 MBit/s and proper DMA for a fast data transfer. The SPE-Adapter as ring master starts after them immediately a transmitted telegram which content is determined by further SPI accesses to the controller. The SPE-Adapter as ring-slave starts further accesses if a telegram is received.

The SPI (Serial Peripheral Interface) is used in two situations:

By default behavior, the SPE card act as slave for the Ring topology. This is necessary, because the controller software may be wrong, and the ring should be work nevertheless. A reset on the controller should be execute a proper state for all other stations in the ring.

But if you have only SPE-slaves in the ring, a faulty received telegram circles in the ring. A master is necessary to break this behavior.

Thats why the master can be selected hard wired. The standard FPGA uses the pin A16 for selecting master = lo or slave = hi (with internal pull up). It means you need a pin header and a jumper to select the master property.

The frame_in is the first important control signal from the controller to the SpeA-card.

In active mode it forces the SPI access.

In passive mode it resets the SPI access to receive the next written word as cmd, see chapter Reset the SPE card to psssive mode for frist cmd

The frame_out signal from the SPE card (output) to the controller is set to active (high) with a receiving telegram after correct received synchronization if the SFD (Start Frame Delimiter) is detected. Because the internal clock in the FPGA is synchronized, this signal have a jitter of typical 10..30 ns only.

This frame_out signal is reset to inactive (low) after receiving the whole telegram. This is either if the clock synchronization is lossed because of a gap between the telegrams, especially for Bus/Multidrop topology, or if the amount of data words are expired for Ring topology. This amount of data words comes either from the first data word, bit 9..0, or also from configuration.

Especially for the gap detection in Bus/Multidrop topology this "end of telegram" information can be used to trigger an interrupt to evaluate the telegram.

For Ring Topology with cyclically communication this is not usefull, instead the PWM should be synchronized, see chapter PLL and its synchronization.

In the master the communication is sent very time deterministically with the falling edge of the frame_in signal. Thereby the internal clock in the FPGA is synchronized to +- 15 ns (jitter 30 ns measured) to the falling clock edge of the frame_Inp.

In the slave the SFD bit (Start Frame Delimiter, last bit of the synchronization pattern) generates the signal frame_out with Lo-Hi transition. This signal gets back to inactive (low) if the telegram is finished.

The simple scheme of time synchronization is:

Thus the master determines the clock, all slaves react. If, however, a slave emits a PWM signal (pulse width modulation) that has a hardware-defined period, then this should be synchronous with the received data or with the time cycle of the master. The same requirement arises for transducers with a cycle of averaging. If no effort would be made in this direction, then the measuring and setting cycles would adjust floating to each other, because the quartz clocks are never exactly the same on longer times. The result would be fluctuating dead times in the closed loop of the control. For simple and slow controls this is no problem (e.g. temperature control of radiators, light brightness or similar). However, this is a disturbing effect for electrical controls that rely on the short cycle time.

Controllers often have PWM modules that are additionally equipped with a so-called "capture" option (capture of the counter status with an input signal). With this possibility, the PWM can be controlled as an actuator in particular, but also with measuring controllers, so that the cycles are stable to each other with low jitter. With regard to crystal accuracy, only standard requirements are to be met, see the example calculation below.

The PWM as a time-determining element is adjusted in its period duration in each cycle with a so-called PLL control (Phase Look Loop). For example, if the crystal frequency of a controller is increased by 0.1%, then instead of a standard 2000 for 50 µs counted with 25 ns, a 2002 is written in, which can jump between 2001 and 2003 depending on the time situation. Thus the own cycle jitters around the resolution of the PLL by +- 25 ns.

If the cycle of the PLL control is used for the internal software of the controller, the measurement, and the output values (for example PWM for electrical valves) have the same synchronized cycle time, but also the jitter. For an integral mean value of measurement signals this can be considered in most cases. An actuator would fluctuate in the per mill range because of the limited resolution, which is usually not a problem. An PWM output may have a "digital noise" due to this jitter in range of lesser 1 %, which is filtered by the natural time constants.

It is important for the SPE communication that the time of the cycle start in the master is transmitted to all slave devices as accurately and jitter-free as possible. For this purpose, the FPGA contains a synchronization of the stepped clock of 100 ns for a bit width of the 10 Mbit/s SPE communication to the frame_in edge in the master and to all receive bits in the slaves. Synchronization takes place during reception of the sync pattern (synchronization bit sequence). The stepped clock is briefly increased or decreased to 9 or 11 crystal clock cycles (10 ns, 100 MHz crystal). This is allowed in the sync pattern. The correction is made up to 5 times distributed over the entire pattern depending on the position of the bit edges. Thus the internal clock is shifted by + or - 50 ns each time. In the further course of the telegram a small deviation is then assumed. This should be less than 2 10 ns cycles for a telegram runtime of 40 µs. This requires a quartz tolerance for the FPGA SPE connections of 20 ns/40 µs = 0.5 ‰, usually observed by standard quartz crystals. For a longer runtime of a telegram, for example at 1500 bytes (1.2 ms), already about 20 ppm crystal accuracy would be required. However, it is also possible to tune the bit width in the telegram between 90..110 ns, with a slightly increased probability of transmission errors.

The meaning of the words of the data link layer accordingly standard IEEE 802.2 are not necessary for a ring topology in a defined manner because the source and destination are defined by the wiring. Also the other data are not necessary if all station understand the changed data frame in the same kind.

Of course it is not possible, also not for tests (for example using Wireshark as test tool) to transmit the data alternatively outside this specific ring.

The change of the meaning of frame data is done firstly to reduce the overhead, because the goal is, communication cycle of down to 50 µs. That allows only 62 Byte in sum inclusively Sync, SFD, CRC, gap.

In the non-gap mode, only possible for ring communication, the gap is summarized with the Sync pattern.

If the telegram cycle has a jitter from up to 1 µs due to controlling oscillations to the PLL control for the cycle time, it changes the number of sync data bits till 21 bit. This is the limit.

The next schema shows the telegram frame, the second line shows the number of bits per element.

For Multidrop Bus or Star topology for a Switch or Router connection a station should be set for receiving firstly to listen on incomming telegrams. This is described in chapter Telegram data words in active mode, expecting a received telegram. If the telegram ends, an interrupt can be generated with the trailing edge of frame_out.

The controller now should evaluate the telegram content. The FPGA on the SPE card does not support that. Because of the full frame for telegram transmission due to OSI level 2 and 3 is received, the destination address should be checked whether this telegram is for the own.

If a transmission is required because it is requested by an incomming telegram, the SPE card should be programmed as SPE master to start the transmission. All data to transmit, also the frame data comes generally from the RAM of the controller via SPI access with DMA. It means the data should be proper prepared.

This occurs in millisec times because the data rate is 10 MBit/s. it is 1.5 ms for a telegram with the full length of 1500 Bytes. A controller should have enough time to prepare such telegram communication.

The PC needs a negotiation about the connection. For standard Ethernet connections this negotiation clarifies the Baud rate, 10 / 100MBit/s or 1 GBit/s, for 10 or 100 Mbit/s the usage of the rx and tx wires, and of course firstly the state of connection itself.

For the 10 Mbit/s it is sufficient that the Source transmits on the tx wire so named NLP pulses: https://en.wikipedia.org/wiki/Autonegotiation. That are positive 100 ns pulses in distance of ~ 16 ms. FLP is not necessary. If only NLP pulses are detected by an Ethernet slot on PC, the baud rate of 10 MBit/s is selected automatically, and the Tx wire is detected. (Older Ethernet Slots needs so named cross-cable, but this is no more true today, it is detected by this NLP pulses which line is used for Rx and which for Tx).

But there is a small problem: If the controller runs as shown in the first image, in an own ring with the PC only as listener, and the PC is connected afterwards, then Tx line transmits already telegrams. Because the telegram sequence is high (1..2 ms), no NLP pulses occurs. Then the PC does not recognize the connection. To connect the PC it is necessary that the ring communication for the controller application stops, then NLPs are transmitted, the connection is established, and then all can work.

A second problem in this constellation is: The PC may transmit sometimes so named ARP telegrams (https://en.wikipedia.org/wiki/Address_Resolution_Protocol) and requests an answer for that. But in this constellation the controller does not receive the ARP telegram, it has not a receive input. Hence this solution can only work if a special solution on PC side, maybe a special SPE switch, exists.

This problems are not given if the PC is completely in the ring, the controller receives also telegrams from the PC. For this solution the following situation is given:

A solution for the connectivity for the closed ring for the controller application is:

Usage a second SPEa card only for the telegram input, the input can control the telegrams from the controller through all measurement and actuator stations in the same way as the only measurement forward to PC solution.

This is in case of the last image in the chapter above. In the normal working mode the controller creates telegrams, which are forwarded from all stations and filled in with data from the measurement stations. The telegram arrives on the PC and can evaluated there. The Controller is always sensitive for command telegrams.

The problematically case is, that the overall association of all stations should answer to the PC with some special telegrams for routing, the so named ARP telegrams. ("Address Resolution Protocol"). An ARP request is received by the controller. The answer should be prepared also by the controller, but forwarded through all stations to the PC. The whole associations of all ring topology stations answers or are seen as only one station with one IP address and one MAC address. Hence, the outer stations should be forwarded the telegram only, without evaluation. The same approach is given for a ping telegram, which should also be possible.

The other stations are prepared normally for receiving a value telegram. It means the data are written in positions in the RAM for measurement data, and also especially data are read and replaced in the telegram with the own measurement data. To prevent doing the same for a ARP or ping telegram the FPGA detects the telegram type and todo detecting content and use switch buffer.

The following scope view shows a for example ARP or also a ping telegram and its answer during transmission of measurement telegrams:

Image: Scope ping telegram

This image shows a ping request (red, left cursor) and its answer (on right cursor). The ping is embedded in a currently transmission of value telegrams of 500 words (1000 byte) in a cycle of 1 ms. The gap between this value telegrams allows other short telegrams between, as shown by the ping answer, as well as of course the necessary ARP telegrams. This telegrams are typically short (lesser than 100 µs inclusively the necessary gap). Hence it possible to regarded them in the whole timing.

As you see here, the received command telegram comes during the transmitted telegram, or after it. This is accidently. There is a only one proplem: If the command telegram arrives the Controller, and yet in this moment (only for a few microseconds) the controller programs its SPI connection newly, the command telegram is not recognized. This command telegram is then lost. But usual a command telegram can be lost, the command should be repeated by the users software as it is familiar for UDP data connection.

Because the command telegram does not need an answer, the answer is the currently running measurement telegrams, no further telegram is transmitted form the controller-meas system.

It is described in SpeA-ControllerSw.html#ExmMeasData

The SPE plugs of the SPE card are standard Harting jacks with two poles for SPE. If you want to connect other jacks, or harting plugs with more pins for power, you can connect it outside the card (maybe mounted above), you can use two soldering points for the SPE signals.

The polarity is primary not defined. The FPGA contains logic to detect with the SFD (Start Frame Delimiter) bit whether the polarity is reversed, and correct it. But the polarity should be well defined especially for PoDL (Power over Data Line), see chapter Power over Data Line (PoDL)

Generally the SPE card is accomplished to the standards of the physical layer. It means shortly potential disturbance of 1.5 kV is possible, and general a potential isolation is given with filtering of disturbances.

Look on this part of the schema:

Right side you see the SPE plug. It has the two SPE pins and a shield. The shield can be connected to the ground of the card using the GNDE-GND4 connection. This is recommended if the SPE card has no other Ground connection, all inputs are potential separated and the grounding of the SPE-card should be done with the shield.

It is not recommended to connect ground and shield if the SPE-card has an own ground connection for example with the cubicle ground or any other ground for due to the connected controller hardware. Two ground connections using really earth connection of via capacitors can force circular currents through the shield. That should be prevented.

Hence it is a carefully descision using the ground bridge depending on the whole wiring situation.

The middle point of the potential isolation transformer is connect with 100 Ohm and 1000 pF/1.5 kV to both the shield and the ground. This should be grounded spikes which are symmetrically on both SPE data lines. The absence of this grounding can lead to higher voltages, which are then passed through on the secondary side, of the potential isolation transformer, to the electronics. It is also a question whether this grounding should connect to the shield or to the ground of the electric circuit. If the shield is connected to ground, it is the same. If the circuit ground is connected to any earth, it is sufficient. But if the circuit ground is potential isolated, and only capacitive connected to any earth, it may be better to remove one of the resistor or capacitor to ground from the card.

Both windings to the primary mid point of the potential isolation transformer are not galvanic connected, instead by a capacitor 470 nF/100 V due to the possibility of Power over Data Line.

The mid of the secondary side of the signal transformer is grounded with 4.7 nF recommended by the manufactor (Würth). Additionally it has a middle voltage of 1.65 V, which is necessary as middle voltage for the difference inputs of the FPGA, and also for the current source output, see chapter Current source for Transmit.

On the secondary side of the potential isolation the 100 Ohm resistor for line terminating is connected. After this a so named "common mode choke" is used. This common mode choke has two reasons:

Last not least a so named TVS Diode as voltage protection for the FPGA inputs is used.

The both signals after the common mode choke parallel to the TVS diode goes immediately then to the differential input of the FPGA. Alternatively for transmission there are driven from the current source left side of the 100 nF capacitors, chapter Current source for Transmit.

The capability to use the two data lines for power supply is one of the benefits of SPE. Usual for "Power over Ethernet" different twisted pairs are used for the power which are isolated one by another because of its own signal transformers. But in SPE there is only one pair and one signal transformer. So a capacitor in the mid point of the both primary winding of the signal transformer separated direct voltages on the line. The PoDL is defined as direct voltage in range of 12V, 24V or 48 V due to several industry standards and automobile. Because 24 V is the widely used industry standard for auxiliary power supply, this is prioritized first.

The power consumption and hence the current should be till 4 A for some applications. But such an high current needs large inductance and also resistor losses of the cables. To figure out a reasonable compromise, the standard assembly allows a max. current of no more as 0.7 A using decoupling chokes from Würth: 744870471 https://www.we-online.com/catalog/datasheet/744870471.pdf. A shortly higher current till 1 A is not an extrem problem. With this values, regarding an undervoltage of 19 V, a power transmission of 13 W is possible. Because a typical small microcontroller circuit needs power in range of 1 W for the board, it is sufficient. But is it too little to supply, for example, a circuit breaker.

Secondly, the ring structure forces that the whole current of all consumer passes all chockes, whereby two chokes are in series per SPE card. The resistance of a winding of this choke is 1 Ohm, max. 1.2 Ohm per Winding. It means one card has 4..5 Ohm. It means if you use 5 cards in the ring, it is 18 Ohm, and the last sink consumes the whole power, furthermore 12 V loss is accepted over the line, you can feed the 0.6 A, but you get only approximately 7 W on the last station. This may be enough for some approaches, but not for all.

If you need more power, the following solutions are possible:

As you see the given solution is for less power consumption < 10 W or in range of 1..2 W per station, but for prototyping an adaption to other solutions is possible.

It seems to be recommended to use the PoDL for the SPE card itself and also for the connected controller card. Expectable power consumptions are in range.

There are two solutions:

The application a) may be often usable. The earth connection may be given by the shield of the SPE cable, the circuit itself is hence near the earth, but not connected to earth immediately in the station. Measurement points may be potential free by itself, for example hall-effect current measurements or measurements after a potential isolated current measurement transformer. It is a topic of capacitive coupling to the environment. Parasitic capacitive currents from the environment flows from the ground to the SPE shield, and then to the earth in that station which has the earth connection from the shield. It means the SPE cable shield gathers all parasitic ground currents. In a disturbing environment you can also box your controller and SPE card in a shield, which is not connected to your ground, but connected to the earth in the cubicle. Hence the influence from the environment or grounded in the cubicle and does not reach your controller board. Then a) is also sufficient.

The image above shows an example for a potential separated current measurement transformer on a controller with SPE card, but with isolated ground, which is housed in an own shield. The circuit itself is shielded, and hence disturbances are grounded with the shield, as a faraday cage. But less disturbance can come over the wired plugs, and in this case over the lesser shielded transformer secondary winding itself. It is of course better to shield the lines too locally grounded, and use so named "feedthrough capacitors", but this is an example to explain the problem. This lesser disturbance current flows over the circuit ground to the connected SPE cable shield, and last not least to the earth on another station. Now it is a question of amount of this disturbance current.

As you see an own isolated ground in a station grounded via the shield is often possible. You should regard other shielding approaches for your station.

The approach b) is the standard for such solution: Potential separated PoDL preparation and a locally grounded ground connection. But for the approach b) you should also think about the shield-ground connection of the SPE cable, see chapter Potential isolation, ground and shield. Do not create currents in loop over the shield!

For the approach a) which is also often sufficient for experience, the SPE card contains a 24 V to 5 V stepdown converter type TSR 1-2450 https://www.tracopower.com/de/deu/model/tsr-1-2450. The minimum input volatage for that is 6.5 V. It means PoDL for 12 V nominal voltage is also possible. The maximal input voltage is 36 V, which is proper for the recommended 24 V nominal supply voltage for PoDL.

Also a 5V to 3.3 V Stepdown converter is part of the SPE card: MP2153GQFU-33-P https://www.mouser.de/datasheet/2/277/MP2153-1624349.pdf. This can be used also for independent (or potential separated) power supply from an independent 5 V source, not from the internal TRACO power.

Last not least you can get both the 5V and also 3.3 V power supply independent of the solution on the SPE card. Look on the wiring possibilities:

As you see also in the image above: There are four diodes for a bridge rectifier. This is not for AC current on the PoDL line, it is for secure the polarity. But if the polarity is clarified (one SPE wire is minus, the other plus), then you need only one diode (recommended) as polarity protection, and a ground wire instead the minus-diode.

The TRACO power TSR-1-2450 is right side of the diodes, it may be removed (manual soldered anyway) if it is not used. The MP2153GQFU-33-P IC with a small choke is right side of that. It is isolated if the connections 5P3 and 3P 3PP on J9 are not given.

See also the circuit schema:

The JTAG pins can be originally connect to a programming adapter via USB from the Trenz company:

https://shop.trenz-electronic.de/de/TE0790-03L-XMOD-FTDI-JTAG-Adapter-nicht-kompatibel-mit-Xilinx-Tools

The JTAG pins can be connected also from other USB adapter.

The row below presents the JTAG Signals. That are connected to the following FPGA pins:

Reset = B29 in the top row is connected with Reset or PROGRAMN of the FPGA = B29. This Pin is with C20 = 100 nF related to GND on switch on. It will be moved to high (3.3 V) with R54 = 10 k. With the resulting time constant of 1 ms the FPGA is still held in reset after reaching VCC_Power. This helps if the VCC comes somewhat unclean in the range < 1 ms. The reset pin discharges the C31 with 470 Ohm and thus also performs a new reset during operation, if the pin has not been assigned otherwise in the FPGA programming.

The pins for RxD, TxD and Led from the Trenz adapter are connected to pins in the FPGA that are user executable. These are not standard functions in the FPGA. Other FTDI adapters also have RxD and TxD, which can be supplied by software in the PC via USB, drivers for COM interfaces. For controllers, these are usually connected to the standard UART interface.

Some of the free pins are test pins of the standard design, but they can be used for own approaches too.

Some pins are outputted on normal soldering points (1.8/0.8 mm) which can be equipped with pin headers.

Some other pins are outputted as small soldering points with 1 mm diameter and 0.4 mm hole. Hence small wires can be carefully soldered there, for own approaches.

The following overview presents which free pins are connected:

The 4 Pins RXDxx are test pins only, they are the signals immediately on the difference inputs on the FPGA.

The pin 5P3EN is also a test pin, let it unconnected (see circuit diagram and IC description).